Speaker
Description
Spin qubits implemented in silicon quantum dots (QDs) are among the most promising candidates for large-scale quantum computing due to their compatibility with CMOS technology and their strong potential for monolithic co-integration with control and readout electronics [1]–[3]. In this context, fully depleted silicon-on-insulator (FDSOI) technology offers unique advantages for quantum–classical integration. Its intrinsic electrostatic control, reduced variability, and the availability of a global back gate enable dynamic tuning of device characteristics [4], providing a powerful knob to optimize both performance and power consumption at cryogenic temperatures [5, 6]. In this work, we present our results on the quantum silicon-on-insulator (QSOI®) technology, inspired by the commercial 28 nm FDSOI process, and modified to address the specific requirements of spin qubit fabrication within a CMOS-compatible platform. Leveraging the industrial maturity of a commercial foundry process, we designed, fabricated and tested both quantum and classical devices on the same wafer. We will focus on the performance of the devices, with two objectives in mind: on the one hand, the development of a cryogenic Process Design Kit (PDK) suitable for quantum integrated circuit design. On the other hand, achieving the quantum regimes in arrays of quantum dots. This work demonstrates that advanced FDSOI technology has the potential to support both high-quality silicon spin qubits and cryogenic CMOS electronics on the same Wafer, establishing a scalable and manufacturable path toward large-scale quantum processors within a standard CMOS ecosystem.